--
-- VHDL Architecture Fietssimulator_lib.NOT_1.test
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp6241)
--          at - 11:48:37  7-07-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_NOT_1 IS
   PORT( 
      a : IN     std_logic;
      y : OUT    std_logic
   );

-- Declarations

END s_NOT_1 ;

--
ARCHITECTURE test OF s_NOT_1 IS
BEGIN
  
  y <= NOT a;
  
END ARCHITECTURE test;

